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Journals in DBLP

IEEE Trans. Computers
2006, volume: 55, number: 2

  1. Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi
    Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:97-98 [Journal]
  2. Andy D. Pimentel, Cagkan Erbas, Simon Polstra
    A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:99-112 [Journal]
  3. Teera Phatrapornnant, Michael J. Pont
    Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:113-124 [Journal]
  4. Moo-Kyoung Chung, Chong-Min Kyung
    Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:125-136 [Journal]
  5. Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose
    InTeRail: A Test Architecture for Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:137-149 [Journal]
  6. Xiaoding Chen, Michael S. Hsiao
    Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:150-162 [Journal]
  7. Subhasish Mitra, Kee Sup Kim
    XPAND: An Efficient Test Stimulus Compression Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:163-173 [Journal]
  8. Andrew B. T. Hopkins, Klaus D. McDonald-Maier
    Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:174-184 [Journal]
  9. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  10. Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose
    Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:199-213 [Journal]
  11. Qun Li, Daniela Rus
    Global Clock Synchronization in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:214-226 [Journal]
  12. Erik Larsson, Zebo Peng
    Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:227-239 [Journal]
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