Journals in DBLP

IEEE Trans. Computers
2003, volume: 52, number: 4

1. Çetin Kaya Koç, Christof Paar
   Guest Editors' Introduction to the Special Section on Cryptographic Hardware and Embedded Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:401-402 [Journal]
   
2. Marco Bucci, Lucia Germani, Raimondo Luzzi, Alessandro Trifiletti, Mario Varanonuovo
   A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:403-409 [Journal]
   
3. Palash Sarkar, Subhamoy Maitra
   Efficient Implementation of Cryptographically Useful 'Large' Boolean Functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:410-417 [Journal]
   
4. Rajendra S. Katti, Joseph Brennan
   Low Complexity Multiplication in a Finite Field Using Ring Representation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:418-427 [Journal]
   
5. Arash Reyhani-Masoleh, M. Anwarul Hasan
   Efficient Multiplication Beyond Optimal Normal Bases. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:428-439 [Journal]
   
6. Colleen O'Rourke, Berk Sunar
   Achieving NTRU with Montgomery Multiplication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:440-448 [Journal]
   
7. Akashi Satoh, Kohji Takano
   A Scalable Dual-Field Elliptic Curve Cryptographic Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:449-460 [Journal]
   
8. Sung-Ming Yen, Seungjoo Kim, Seongan Lim, Sang-Jae Moon
   RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:461-472 [Journal]
   
9. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
   Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:4, pp:473-482 [Journal]
   
10. Stefan Mangard, Manfred Josef Aigner, Sandra Dominikus
    A Highly Regular and Scalable AES Hardware Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:483-491 [Journal]
    
11. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:492-505 [Journal]
    
12. Tei-Wei Kuo, Yuan-Ting Kao, Chin-Fu Kuo
    Two-Version Based Concurrency Control and Recovery in Real-Time Client/Server Databases. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:506-524 [Journal]
    
13. Laurence E. LaForge, Kirk F. Korver, M. Sami Fadali
    What Designers of Bus and Network Architectures Should Know about Hypercubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:525-544 [Journal]