Journals in DBLP

IEEE Trans. Computers
1996, volume: 45, number: 8

1. Nicholas S. Bowen, Dhiraj K. Pradhan
   The Effect of Program Behavior on Fault Observability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:868-880 [Journal]
   
2. Charles R. Yount, Daniel P. Siewiorek
   A Methodology for the Rapid Injection of Transient Hardware Errors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:881-891 [Journal]
   
3. Arun K. Somani, Ofer Peleg
   On Diagnosability of Large Fault Sets in Regular Topology-Based Computer Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:892-903 [Journal]
   
4. Amitava Majumdar
   On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:904-916 [Journal]
   
5. José Salinas, Yinan N. Shen, Fabrizio Lombardi
   A Sweeping Line Approach to Interconnect Testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:917-929 [Journal]
   
6. Jacob Savir
   Reducing the MISR Size. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:930-938 [Journal]
   
7. Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
   Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:939-949 [Journal]
   
8. Ronald D. Blanton, John P. Hayes
   Testability of Convergent Tree Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:950-963 [Journal]
   
9. Priyalal Kulasinghe, Ahmed El-Amawy
   Optimal Realization of Sets of Interconnection Functions on Synchronous Multiple Bus Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:8, pp:964-969 [Journal]
   
10. S. Rai, V. P. Kirpalani
    A Modified TRAM Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:969-974 [Journal]
    
11. D. Todd Smith, Barry W. Johnson, Joseph A. Profeta III
    System Dependability Evaluation via a Fault List Generation Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:974-979 [Journal]
    
12. Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili
    Augmented Binary Hypercube: A New Architecture for Processor Management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:980-984 [Journal]
    
13. Sreejit Chakravarty
    A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:985-991 [Journal]