Journals in DBLP
Nicholas S. Bowen , Dhiraj K. Pradhan The Effect of Program Behavior on Fault Observability. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:868-880 [Journal ] Charles R. Yount , Daniel P. Siewiorek A Methodology for the Rapid Injection of Transient Hardware Errors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:881-891 [Journal ] Arun K. Somani , Ofer Peleg On Diagnosability of Large Fault Sets in Regular Topology-Based Computer Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:892-903 [Journal ] Amitava Majumdar On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:904-916 [Journal ] José Salinas , Yinan N. Shen , Fabrizio Lombardi A Sweeping Line Approach to Interconnect Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:917-929 [Journal ] Jacob Savir Reducing the MISR Size. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:930-938 [Journal ] Sanjay Gupta , Janusz Rajski , Jerzy Tyszer Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:939-949 [Journal ] Ronald D. Blanton , John P. Hayes Testability of Convergent Tree Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:950-963 [Journal ] Priyalal Kulasinghe , Ahmed El-Amawy Optimal Realization of Sets of Interconnection Functions on Synchronous Multiple Bus Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:964-969 [Journal ] S. Rai , V. P. Kirpalani A Modified TRAM Architecture. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:969-974 [Journal ] D. Todd Smith , Barry W. Johnson , Joseph A. Profeta III System Dependability Evaluation via a Fault List Generation Algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:974-979 [Journal ] Hari Lalgudi , Ian F. Akyildiz , Sudhakar Yalamanchili Augmented Binary Hypercube: A New Architecture for Processor Management. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:980-984 [Journal ] Sreejit Chakravarty A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:985-991 [Journal ]