Journals in DBLP

IEEE Trans. Computers
1993, volume: 42, number: 9

1. P. David Fisher, Sheng-Fu Wu
   Race-Free State Assignment for Synthesizing Large-Scale Asynchronous Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1025-1034 [Journal]
   
2. Mark G. Karpovsky, Saeed M. Chaudhry
   Design of Self-Diagnostic Boards by Multiple Signature Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1035-1044 [Journal]
   
3. William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
   The Effect of Code Expanding Optimizations on Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1045-1057 [Journal]
   
4. Jürgen Götze, Steffen Paul, Matthias Sauer
   An Efficient Jacobi-like Algorithm for Parallel Eigenvalue Computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1058-1065 [Journal]
   
5. Irith Pomeranz, Sudhakar M. Reddy
   Classification of Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1066-1077 [Journal]
   
6. Jong Kim, Kang G. Shin
   Deadlock-Free Fault-Tolerant Routing in Injured Hypercubes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1078-1088 [Journal]
   
7. Jehoshua Bruck, Robert Cypher, Ching-Tien Ho
   Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1089-1104 [Journal]
   
8. Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault
   Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1105-1120 [Journal]
   
9. Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
   Optimal Configuring of Multiple Scan Chains. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1993, v:42, n:9, pp:1121-1131 [Journal]
   
10. William A. Porter, Xiaoyan Zheng
    A Nonbinary Neural Network Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1132-1135 [Journal]
    
11. Yung-Yuan Chen, Shambhu J. Upadhyaya
    Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1136-1141 [Journal]
    
12. Chin-Liang Wang, Jung-Lung Lin
    A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1141-1146 [Journal]
    
13. Kien A. Hua, Lishing Liu, Jih-Kwon Peir
    Designing High-Performance Processors Using Real Address Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1146-1151 [Journal]
    
14. Masakatu Morii, Kazuhiko Iwasaki
    A Note on Aliasing Probability for Multiple Input Signature Analyzer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1152- [Journal]