Journals in DBLP

IEEE Trans. Computers
1994, volume: 43, number: 4

1. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
   Innovative Structures for CMOS Combinational Gates Synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:385-399 [Journal]
   
2. Jien-Chung Lo
   Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:400-412 [Journal]
   
3. John C. Ramirez, Rami G. Melhem
   Computational Arrays with Flexible Redundancy. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:413-430 [Journal]
   
4. Pradeep K. Dubey, George B. Adams III, Michael J. Flynn
   Instruction Window Size Trade-Offs and Characterization of Program Parallelism. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:431-442 [Journal]
   
5. Michael J. Corinthios
   Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:443-459 [Journal]
   
6. Vitit Kantabutra, Andreas G. Andreou
   A State Assignment Approach to Asynchronous CMOS Circuit Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:460-469 [Journal]
   
7. Annette Lagman, Walid A. Najjar, Pradip K. Srimani
   An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:470-475 [Journal]
   
8. Shambhu J. Upadhyaya, Bina Ramamurthy
   Concurrent Process Monitoring with No Reference Signatures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:475-480 [Journal]
   
9. Imrich Chlamtac, András Faragó
   An Optimal Channel Access Protocol with Multiple Reception Capacity. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:4, pp:480-484 [Journal]
   
10. Shlomo Kipnis
    Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:484-489 [Journal]
    
11. Steven W. Burns, Niraj K. Jha
    A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:490-495 [Journal]
    
12. Shih-Yuang Su, Cheng-Wen Wu
    Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:495-501 [Journal]
    
13. Spencer W. Ng, Richard L. Mattson
    Uniform Parity Group Distribution in Disk Arrays with Multiple Failures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:501-506 [Journal]
    
14. Chien-In Henry Chen, Anup Kumar
    Comments on "Area-Time Optimal Adder Design". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:507-512 [Journal]