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Journals in DBLP

IEEE Trans. Computers
1996, volume: 45, number: 1

  1. S. Nandi, Parimal Pal Chaudhuri
    Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:1-12 [Journal]
  2. Rajendra S. Katti
    A New Residue Arithmetic Error Correction Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:13-19 [Journal]
  3. Irith Pomeranz, Sudhakar M. Reddy
    On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:20-32 [Journal]
  4. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Generalized Reed-Muller Forms as a Tool to Detect Symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:33-40 [Journal]
  5. Jovan Dj. Golic
    Linear Models for Keystream Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:41-49 [Journal]
  6. Irith Pomeranz, Sudhakar M. Reddy
    On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:50-62 [Journal]
  7. Sandeep K. Gupta, Dhiraj K. Pradhan
    Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:63-73 [Journal]
  8. Dimitrios Kagaris, Spyros Tragoudas
    Retiming-Based Partial Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:75-87 [Journal]
  9. Oliver Shiu-sing Choy, Lap-kong Chan, Ray Chan, Cheong F. Chan
    Test Generation with Dynamic Probe Points in High Observability Testing Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:88-96 [Journal]
  10. Qing Hu, Xiaojun Shen, Weifa Liang
    Optimally Routing LC Permutations on k-Extra-Stage Cube-Type Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:97-103 [Journal]
  11. Chi-Sung Laih, Ching-Nung Yang
    On the Analysis and Design of Group Theoretical T-syEC/AUED Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:103-108 [Journal]
  12. Michael D. Smith, Pinaki Mazumder
    Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:109-115 [Journal]
  13. Suresh Rai, Weian Deng
    Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:115-121 [Journal]
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