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Journals in DBLP

IEEE Trans. Computers
1983, volume: 32, number: 9

  1. Witold S. Wojciechowski, Anthony S. Wojcik
    Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:785-798 [Journal]
  2. Timothy C. K. Chou, Jacob A. Abraham
    Load Redistribution Under Failure in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:799-808 [Journal]
  3. Thomas F. Schwab, Stephen S. Yau
    An Algebraic Model of Fault-Masking Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:809-825 [Journal]
  4. Quentin F. Stout
    Mesh-Connected Computers with Broadcasting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:826-830 [Journal]
  5. James E. Smith, Paklin Lam
    A Theory of Totally Self-Checking System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:831-844 [Journal]
  6. Inder S. Gopal, Don Coppersmith, C. K. Wong
    Optimal Wiring of Movable Terminals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:845-858 [Journal]
  7. Makoto Kobayashi
    Dynamic Profile of Instruction Sequences for the IBM System/370. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:859-861 [Journal]
  8. Leslie G. Valiant
    Optimality of a Two-Phase Strategy for Routing in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:861-863 [Journal]
  9. Chamarty D. V. P. Rao, Nripendra N. Biswas
    On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:863-868 [Journal]
  10. Martin de Prycker
    Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:868-872 [Journal]
  11. Murali R. Varanasi, T. R. N. Rao, Son Pham
    Memory Package Error Detection and Correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:872-874 [Journal]
  12. Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao
    A Parallel Architecture for Digital Filtering Using Fermat Number Transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:874-877 [Journal]
  13. R. Gnanasekaran
    On a Bit-Serial Input and Bit-Serial Output Multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:878-880 [Journal]
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