Journals in DBLP

IEEE Trans. Computers
1999, volume: 48, number: 2

1. Veljko M. Milutinovic, Mateo Valero
   Enhancing and Exploiting the Locality. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:97-99 [Journal]
   
2. Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith
   Functional Implementation Techniques for CPU Cache Memories. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:100-110 [Journal]
   
3. Eric Rotenberg, Steve Bennett, James E. Smith
   A Trace Cache Microarchitecture and Evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:111-120 [Journal]
   
4. Doug Joseph, Dirk Grunwald
   Prefetching Using Markov Predictors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:121-133 [Journal]
   
5. Chi-Keung Luk, Todd C. Mowry
   Automatic Compiler-Inserted Prefetching for Pointer-Based Applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:134-141 [Journal]
   
6. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
   Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:142-149 [Journal]
   
7. Olivier Temam
   An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:150-158 [Journal]
   
8. Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary
   Improving Cache Locality by a Combination of Loop and Data Transformation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:159-167 [Journal]
   
9. John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis
   Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1999, v:48, n:2, pp:168-175 [Journal]
   
10. Hantak Kwak, Ben Lee, Ali R. Hurson, Suk-Han Yoon, Woo-Jong Hahn
    Effects of Multithreading on Cache Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:176-184 [Journal]
    
11. Nigel P. Topham, Antonio González
    Randomized Cache Placement for Eliminating Conflicts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:185-192 [Journal]
    
12. Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt
    Evaluation of Design Options for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:193-204 [Journal]
    
13. Mark Heinrich, Vijayaraghavan Soundararajan, John L. Hennessy, Anoop Gupta
    A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:205-217 [Journal]
    
14. Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve
    The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:218-226 [Journal]
    
15. Seungjoon Park, David L. Dill
    An Executable Specification and Verifier for Relaxed Memory Order. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:227-235 [Journal]
    
16. Donglai Dai, Dhabaleswar K. Panda
    Exploiting the Benefits of Multiple-Path Network DSM Systems: Architectural Alternatives and Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:236-244 [Journal]
    
17. Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim
    Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:245-255 [Journal]
    
18. Zheng Zhang, Marcelo H. Cintra, Josep Torrellas
    Excel-NUMA: Toward Programmability, Simplicity, and High Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:256-264 [Journal]