Journals in DBLP

IEEE Trans. Computers
2007, volume: 56, number: 3

1. Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan
   Lightweight Error Correction Coding for System-Level Interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:289-304 [Journal]
   
2. Majid Khabbazian, T. Aaron Gulliver, Vijay K. Bhargava
   Double Point Compression with Applications to Speeding Up Random Point Multiplication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:305-313 [Journal]
   
3. Kirk W. Cameron, Rong Ge, Xian-He Sun
   log_nP and log₃P: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:314-327 [Journal]
   
4. Yutao Zhong, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding
   Miss Rate Prediction Across Program Inputs and Cache Configurations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:328-343 [Journal]
   
5. Fumiko Harada, Toshimitsu Ushio, Yukikazu Nakamoto
   Adaptive Resource Allocation Control for Fair QoS Management. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:344-357 [Journal]
   
6. Xiliang Zhong, Cheng-Zhong Xu
   Energy-Aware Modeling and Scheduling for Dynamic Voltage Scaling with Statistical Real-Time Guarantee. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:358-372 [Journal]
   
7. Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen
   Space-Optimal, Wait-Free Real-Time Synchronization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:373-384 [Journal]
   
8. Umut Balli, Haisang Wu, Binoy Ravindran, Jonathan Stephen Anderson, E. Douglas Jensen
   Utility Accrual Real-Time Scheduling under Variable Cost Functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:385-401 [Journal]
   
9. James Chien-Mo Li, Hung-Mao Lin, Fang-Min Wang
   Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:3, pp:402-414 [Journal]
   
10. Cecilia Metra, Daniele Rossi, T. M. Mak
    Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:3, pp:415-428 [Journal]
    
11. K. Wendy Tang, Ridha Kamoua
    An Upper Bound for the Bisection Width of a Diagonal Mesh. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:3, pp:429-431 [Journal]