Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 9

1. Narayan R. Aluru, Kincho H. Law, Robert W. Dutton
   Simulation of the hydrodynamic device model on distributed memory parallel computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1029-1047 [Journal]
   
2. Hyung Ki Lee, Dong Sam Ha
   HOPE: an efficient parallel fault simulator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1048-1058 [Journal]
   
3. Jaewon Kim, Sung-Mo Kang
   A new triple-layer OTC channel router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1059-1070 [Journal]
   
4. Chennian Di, Jochen A. G. Jess
   An efficient CMOS bridging fault simulator: with SPICE accuracy. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1071-1080 [Journal]
   
5. Manoj Franklin, Kewal K. Saluja
   Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1081-1087 [Journal]
   
6. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
   Fast true delay estimation during high level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1088-1105 [Journal]
   
7. Qing Zhu, Wayne Wei-Ming Dai
   High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1106-1118 [Journal]
   
8. Guy Bois, Eduard Cerny
   Efficient generation of diagonal constraints for 2-D mask compaction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1119-1126 [Journal]
   
9. Mohankumar Guruswamy, Martin D. F. Wong
   Echelon: a multilayer detailed area router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1126-1136 [Journal]
   
10. Per Larsson-Edefors
    Technology mapping onto very-high-speed standard CMOS hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1137-1144 [Journal]
    
11. Jaushin Lee, Janak H. Patel
    Hierarchical test generation under architectural level functional constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1144-1151 [Journal]
    
12. Mario A. Lopez, Ravi Janardan, Sartaj K. Sahni
    Efficient net extraction for restricted orientation designs [VLSI layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1151-1159 [Journal]
    
13. Piyush K. Sancheti, Sachin S. Sapatnekar
    Optimal design of macrocells for low power and high speed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1160-1166 [Journal]
    
14. Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Combinational test generation using satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1167-1176 [Journal]
    
15. Massoud Pedram, Sasan Iman
    Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1176- [Journal]