Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 4

1. Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill
   Symbolic model checking for sequential circuit verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:401-424 [Journal]
   
2. Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
   A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:425-438 [Journal]
   
3. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
   A transformation-based method for loop folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:439-450 [Journal]
   
4. Minjoong Rim, Rajiv Jain
   Lower-bound performance estimation for the high-level synthesis scheduling problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:451-458 [Journal]
   
5. Mark Aagaard, Miriam Leeser
   PBS: proven Boolean simplification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:459-470 [Journal]
   
6. Ahmed S. Desouki, Young-June Park, Hong-Shick Min
   A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:471-481 [Journal]
   
7. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
   Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:482-493 [Journal]
   
8. Rupert Howes, William Redman-White, Ken G. Nichols, Peter J. Mole, Michael J. Robinson, Simon Bird
   An SOS MOSFET model based on calculation of the surface potential. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:494-506 [Journal]
   
9. Tatsuya Kunikiyo, Katsuyoshi Mitsui, Masato Fujinaga, Tetsuya Uchida, Norihiko Kotani
   Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:507-514 [Journal]
   
10. Henry Cox, Janusz Rajski
    On necessary and nonconflicting assignments in algorithmic test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:515-530 [Journal]
    
11. Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
    Fault simulation for multiple faults by Boolean function manipulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:531-535 [Journal]