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IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 6

  1. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
    Multilevel symmetry-constraint generation for retargeting large analog layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:945-960 [Journal]
  2. Shih-Hsu Huang, Yow-Tyng Nieh
    Synthesis of nonzero clock skew circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:961-976 [Journal]
  3. Alan Mishchenko, Robert K. Brayton
    A theory of nondeterministic networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:977-999 [Journal]
  4. Vivek V. Shende, Stephen S. Bullock, Igor L. Markov
    Synthesis of quantum-logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1000-1010 [Journal]
  5. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Linear cofactor relationships in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1011-1023 [Journal]
  6. Ravindra Jejurikar, Rajesh K. Gupta
    Energy-aware task scheduling with task synchronization for embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1024-1037 [Journal]
  7. Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
    Impact of stress-induced backflow on full-chip electromigration risk assessment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1038-1046 [Journal]
  8. Junjun Li, S. Joshi, R. Barnes, E. Rosenbaum
    Compact modeling of on-chip ESD protection devices using Verilog-A. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1047-1063 [Journal]
  9. Debjit Sinha, Hai Zhou
    Gate-size optimization under timing constraints for coupling-noise reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1064-1074 [Journal]
  10. Peter G. Sassone, Sung Kyu Lim
    Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1075-1086 [Journal]
  11. Zhao Li, C.-J. Richard Shi
    SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1087-1103 [Journal]
  12. Tao Jiang, R. D. (Shawn) Blanton
    Inductive fault analysis of surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1104-1116 [Journal]
  13. Manan Syal, Michael S. Hsiao
    New techniques for untestable fault identification in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1117-1131 [Journal]
  14. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    Three-dimensional place and route for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1132-1140 [Journal]
  15. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1140-1145 [Journal]
  16. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  17. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A high-performance data path for synthesizing DSP kernels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1154-1162 [Journal]
  18. Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri
    Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1163-1169 [Journal]
  19. Irith Pomeranz, Sudhakar M. Reddy
    Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1170-1175 [Journal]
  20. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via crosslinks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1176-1182 [Journal]
  21. Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1183-1191 [Journal]
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