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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 2

  1. Gerhard Tröster, Peter Tomaszewski
    Mismatch simulation for layout sensitive parameters of IC components and devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:101-107 [Journal]
  2. Eddie van Schie, Jan Middelhoek
    Two methods to improve the performance of Monte Carlo simulations of ion implantation in amorphous targets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:108-113 [Journal]
  3. Linda S. Milor, V. Visvanathan
    Detection of catastrophic faults in analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:114-130 [Journal]
  4. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    A directed search method for test generation using a concurrent simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:131-138 [Journal]
  5. Shmuel Wimer, Israel Koren, Israel Cederbaum
    Optimal aspect ratios of building blocks in VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:139-145 [Journal]
  6. Gopalakrishnan Vijayan, H. H. Chen, Chak-Kuen Wong
    On VHV-routing in channels with irregular boundaries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:146-152 [Journal]
  7. Rainer Amann, Utz G. Baitinger
    Optimal state chains and state codes in finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:153-170 [Journal]
  8. Raul Camposano, Wolfgang Rosenstiel
    Synthesizing circuits from behavioural descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:171-180 [Journal]
  9. Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli
    Logic verification algorithms and their parallel implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:181-189 [Journal]
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