Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 1

1. H. Fujiwara
   A design of programmable logic arrays with random pattern-testability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:5-10 [Journal]
   
2. Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
   Methodologies for testing embedded content addressable memories. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:11-20 [Journal]
   
3. Shek-Wayne Chan, Chin-Long Wey
   The design of concurrent error diagnosable systolic arrays for band matrix multiplications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:21-37 [Journal]
   
4. Larry Carter, Leendert M. Huisman, Tom W. Williams
   TRIM: testability range by ignoring the memory. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:38-49 [Journal]
   
5. Dick L. Liu, Edward J. McCluskey
   Design of large embedded CMOS PLAs for built-in self-test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:50-59 [Journal]
   
6. Shambhu J. Upadhyaya, Kewal K. Saluja
   A new approach to the design of built-in self-testing PLAs for high fault coverage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:60-67 [Journal]
   
7. Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner
   Probability models for pseudorandom test sequences. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:68-74 [Journal]
   
8. Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke
   Bounds and analysis of aliasing errors in linear feedback shift registers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:75-83 [Journal]
   
9. K. Iwasaki
   Analysis and proposal of signature circuits for LSI testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:84-90 [Journal]
   
10. Laung-Terng Wang, Edward J. McCluskey
    Hybrid designs generating maximum-length sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:91-99 [Journal]
    
11. Joseph L. A. Hughes
    Multiple fault detection using single fault test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:100-108 [Journal]
    
12. Niraj K. Jha
    Testing for multiple faults in domino-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:109-116 [Journal]
    
13. Ronald J. Cosentino
    Concurrent error correction in systolic architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:117-125 [Journal]
    
14. Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert
    SOCRATES: a highly efficient automatic test pattern generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:126-137 [Journal]
    
15. Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland
    Logic design verification via test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:138-148 [Journal]