Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 9

1. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
   Solving difficult instances of Boolean satisfiability in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1117-1137 [Journal]
   
2. Hao Zheng, Eric Mercer, Chris J. Myers
   Modular verification of timed circuits using automatic abstraction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1138-1153 [Journal]
   
3. Armita Peymandoust, Giovanni De Micheli
   Application of symbolic computer algebra in high-level data-flow synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1154-1165 [Journal]
   
4. Debatosh Debnath, Zvonko G. Vranesic
   A fast algorithm for OR-AND-OR synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1166-1176 [Journal]
   
5. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
   Technology-portable analytical model for DSM CMOS inverter transition-time estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1177-1187 [Journal]
   
6. Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
   Probabilistic analysis of interconnect coupling noise. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1188-1203 [Journal]
   
7. Thomas Binder, Andreas Hössinger, Siegfried Selberherr
   Rigorous integration of semiconductor process and device simulators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1204-1214 [Journal]
   
8. Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
   Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1215-1227 [Journal]
   
9. Gang Li, Narayan R. Aluru
   Efficient mixed-domain analysis of electrostatic MEMS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1228-1242 [Journal]
   
10. Aseem Agarwal, Vladimir Zolotov, David T. Blaauw
    Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1243-1260 [Journal]
    
11. Hai Zhou
    Timing analysis with crosstalk is a fixpoint on a complete lattice. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1261-1269 [Journal]
    
12. Soha Hassoun, Christopher Cromer, Eduardo Calvillo-Gámez
    Static timing analysis for level-clocked circuits in the presence of crosstalk. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1270-1277 [Journal]
    
13. Darko Kirovski, Miodrag Potkonjak
    Local watermarks: methodology and application to behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1277-1283 [Journal]
    
14. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    A simulation framework for energy-consumption analysis of OS-driven embedded applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1284-1294 [Journal]