Shiuh-Wuu Lee Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:724-730 [Journal]
Niraj K. Jha A totally self-checking checker for Borden's code. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:731-736 [Journal]
Min-You Wu, Ibrahim N. Hajj Switching network logic approach to sequential MOS circuit design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:782-794 [Journal]
H. Cai On empty rooms in floorplan graphics: comments on a deficiency in two papers. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:795-797 [Journal]
Doron Drusinsky, David Harel Using statecharts for hardware description and synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:798-807 [Journal]
Michael H. Schulz, Elisabeth Auth Improved deterministic test pattern generation with applications to redundancy identification. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:811-816 [Journal]
H. L. Kwok Threshold voltage for GaAs MESFET with a recoil-implanted channel profile. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:817-820 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP