Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 7

1. Paul J. V. Vandeloo, Willy M. C. Sansen
   Modeling of the MOS transistor for high frequency analog design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:713-723 [Journal]
   
2. Shiuh-Wuu Lee
   Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:724-730 [Journal]
   
3. Niraj K. Jha
   A totally self-checking checker for Borden's code. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:731-736 [Journal]
   
4. Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer
   Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:737-743 [Journal]
   
5. Charles J. Poirier
   Excellerator: custom CMOS leaf cell layout generator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:744-755 [Journal]
   
6. Shuo Huang, Omar Wing
   Gate matrix partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:756-767 [Journal]
   
7. Srinivas Devadas, A. Richard Newton
   Algorithms for hardware allocation in data path synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:768-781 [Journal]
   
8. Min-You Wu, Ibrahim N. Hajj
   Switching network logic approach to sequential MOS circuit design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:782-794 [Journal]
   
9. H. Cai
   On empty rooms in floorplan graphics: comments on a deficiency in two papers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:795-797 [Journal]
   
10. Doron Drusinsky, David Harel
    Using statecharts for hardware description and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:798-807 [Journal]
    
11. Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana
    Limitations of switch level analysis for bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:807-811 [Journal]
    
12. Michael H. Schulz, Elisabeth Auth
    Improved deterministic test pattern generation with applications to redundancy identification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:811-816 [Journal]
    
13. H. L. Kwok
    Threshold voltage for GaAs MESFET with a recoil-implanted channel profile. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:817-820 [Journal]