Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 8

1. Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
   Consistency checking and optimization of macromodels. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:957-967 [Journal]
   
2. Silvano Gai, Pier Luca Montessoro
   The fault dropping problem in concurrent event-driven simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:968-971 [Journal]
   
3. Jason Cong, C. L. Liu
   On the k-layer planar subset and topological via minimization problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:972-981 [Journal]
   
4. Yoichi Shiraishi, Jun'ya Sakemi, Kazuyuki Fukuda
   Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:982-993 [Journal]
   
5. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
   LiB: a CMOS cell compiler. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:994-1005 [Journal]
   
6. Hany L. Abdel-Malek, Abdel-Karim S. O. Hassan
   The ellipsoidal technique for design centering and region approximation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1006-1014 [Journal]
   
7. Michael J. Van der Tol, Savvas G. Chamberlain
   Buried-channel MOSFET model for SPICE. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1015-1035 [Journal]
   
8. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
   Design of robustly testable combinational logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1036-1048 [Journal]
   
9. Andrzej J. Strojwas, Stephen W. Director
   An efficient algorithm for parametric fault simulation of monolithic IC's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1049-1058 [Journal]
   
10. C. Leonard Berman
    Circuit width, register allocation, and ordered binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1059-1066 [Journal]
    
11. Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel density reduction by routing over the cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1067-1071 [Journal]
    
12. Giuseppe Caruso
    Near optimal factorization of Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1072-1078 [Journal]
    
13. Pak K. Chan
    Comments on `Asymptotic waveform evaluation for timing analysis'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1078-1079 [Journal]