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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 5

  1. Wendy Belluomini, Chris J. Myers
    Timed state space exploration using POSETs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:501-520 [Journal]
  2. Christoph Meinel, Fabio Somenzi, Thorsten Theobald
    Linear sifting of decision diagrams and its application insynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:521-533 [Journal]
  3. Shantanu Dutt, Wenyong Deng
    Probability-based approaches to VLSI circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:534-549 [Journal]
  4. Sachin S. Sapatnekar
    A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:550-559 [Journal]
  5. Andreas Hössinger, Erasmus Langer, Siegfried Selberherr
    Parallelization of a Monte Carlo ion implantation simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:560-567 [Journal]
  6. Sreejit Chakravarty, Sujit T. Zachariah
    STBM: a fast algorithm to simulate IDDQ tests forleakage faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:568-576 [Journal]
  7. Kun-Jin Lin, Cheng-Wen Wu
    Testing content-addressable memories using functional fault modelsand march-like algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:577-588 [Journal]
  8. Irith Pomeranz, Sudhakar M. Reddy
    A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:589-600 [Journal]
  9. Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti
    Model checking on timed-event structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:601-611 [Journal]
  10. Jun Dong Cho
    Wiring space and length estimation in two-dimensional arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:612-615 [Journal]
  11. Taewhan Kim, Junhyung Um
    A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:615-624 [Journal]
  12. Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang
    Wire space estimation and routability analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:624-628 [Journal]
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