Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 11

1. Darko Kirovski, Miodrag Potkonjak, Lisa Guerra
   Improving the observability and controllability of datapaths foremulation-based debugging. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1529-1541 [Journal]
   
2. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
   An efficient filter-based approach for combinational verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1542-1557 [Journal]
   
3. Asen Asenov, Andrew R. Brown, John H. Davies, Subhash Saini
   Hierarchical approach to "atomistic" 3-D MOSFET simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1558-1565 [Journal]
   
4. Mario Netzel, Bernd Heinemann, Maik Brett, Dagmar Schipanski
   Methods for generating and editing merged isotropic/anisotropic triangular-element meshes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1566-1576 [Journal]
   
5. Ganesh Lakshminarayana, Niraj K. Jha
   FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1577-1594 [Journal]
   
6. Jason Cong, Chang Wu
   Optimal FPGA mapping and retiming with efficient initial state computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1595-1607 [Journal]
   
7. David L. Harris, Mark Horowitz, Dean Liu
   Timing analysis including clock skew. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1608-1618 [Journal]
   
8. Jorge M. Pena, Arlindo L. Oliveira
   A new algorithm for exact reduction of incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1619-1632 [Journal]
   
9. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
   Buffer insertion for noise and delay optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1633-1645 [Journal]
   
10. Toshiyuki Hama, Hiroaki Etoh
    Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1646-1653 [Journal]
    
11. Hany L. Abdel-Malek, Abdel-Karim S. O. Hassan, Mohamed H. Heaba
    A boundary gradient search technique and its applications in design centering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1654-1660 [Journal]
    
12. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A low overhead design for testability and test generation technique for core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1661-1676 [Journal]
    
13. Von-Kyoung Kim, Tom Chen
    On comparing functional fault coverage and defect coverage for memory testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1676-1683 [Journal]
    
14. Hai Zhou, Martin D. F. Wong
    Global routing with crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1683-1688 [Journal]