Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 8

1. David T. Blaauw, Luciano Lavagno
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:962-963 [Journal]
   
2. Armita Peymandoust, Tajana Simunic, Giovanni De Micheli
   Complex instruction and software library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:964-975 [Journal]
   
3. Yoonseo Choi, Taewhan Kim
   Address assignment in DSP code generation - an integrated approach. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:976-984 [Journal]
   
4. Michael J. Wirthlin, Brian McMurtrey
   Web-based IP evaluation and distribution using applets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:985-994 [Journal]
   
5. Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
   Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:995-1004 [Journal]
   
6. Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
   Three-level logic minimization based on function regularities. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1005-1016 [Journal]
   
7. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
   Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1017-1026 [Journal]
   
8. Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
   Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1027-1041 [Journal]
   
9. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
   Design automation with mixtures of proof strategies for propositional logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1042-1048 [Journal]
   
10. Kenneth Francken, Georges G. E. Gielen
    A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1049-1061 [Journal]
    
11. Gang Quan, Xiaobo Sharon Hu
    Minimal energy fixed-priority scheduling for variable voltage processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1062-1071 [Journal]
    
12. Paolo Pavan, Luca Larcher, Massimiliano Cuozzo, Paola Zuliani, Antonino Conte
    A complete model of E²PROM memory cells for circuit simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1072-1079 [Journal]
    
13. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    PROPTEST: a property-based test generator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1080-1091 [Journal]
    
14. Irith Pomeranz, Sudhakar M. Reddy
    Theorems for identifying undetectable faults in partial-scan circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1092-1097 [Journal]
    
15. Joon-Jea Sung, Guen-Soon Kang, Suki Kim
    A transient noise model for frequency-dependent noise sources. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1097-1104 [Journal]
    
16. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
    A test evaluation technique for VLSI circuits using register-transfer level fault modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1104-1113 [Journal]