Journals in DBLP
David T. Blaauw , Luciano Lavagno Guest Editorial. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:962-963 [Journal ] Armita Peymandoust , Tajana Simunic , Giovanni De Micheli Complex instruction and software library mapping for embedded software using symbolic algebra. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:964-975 [Journal ] Yoonseo Choi , Taewhan Kim Address assignment in DSP code generation - an integrated approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:976-984 [Journal ] Michael J. Wirthlin , Brian McMurtrey Web-based IP evaluation and distribution using applets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:985-994 [Journal ] Fadi A. Aloul , Brian D. Sierawski , Karem A. Sakallah Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:995-1004 [Journal ] Anna Bernasconi , Valentina Ciriani , Fabrizio Luccio , Linda Pagli Three-level logic minimization based on function regularities. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1005-1016 [Journal ] Piet Vanassche , Georges G. E. Gielen , Willy M. C. Sansen Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1017-1026 [Journal ] Joel R. Phillips , Luca Daniel , Luis Miguel Silveira Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1027-1041 [Journal ] Gunnar Andersson , Per Bjesse , Byron Cook , Ziyad Hanna Design automation with mixtures of proof strategies for propositional logic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1042-1048 [Journal ] Kenneth Francken , Georges G. E. Gielen A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1049-1061 [Journal ] Gang Quan , Xiaobo Sharon Hu Minimal energy fixed-priority scheduling for variable voltage processors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1062-1071 [Journal ] Paolo Pavan , Luca Larcher , Massimiliano Cuozzo , Paola Zuliani , Antonino Conte A complete model of E2 PROM memory cells for circuit simulations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1072-1079 [Journal ] Ruifeng Guo , Sudhakar M. Reddy , Irith Pomeranz PROPTEST: a property-based test generator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1080-1091 [Journal ] Irith Pomeranz , Sudhakar M. Reddy Theorems for identifying undetectable faults in partial-scan circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1092-1097 [Journal ] Joon-Jea Sung , Guen-Soon Kang , Suki Kim A transient noise model for frequency-dependent noise sources. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1097-1104 [Journal ] Pradip A. Thaker , Vishwani D. Agrawal , Mona E. Zaghloul A test evaluation technique for VLSI circuits using register-transfer level fault modeling. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1104-1113 [Journal ]