The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 12

  1. Miriam Leeser
    Reasoning about the function and timing of integrated circuits with interval temporal logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1233-1246 [Journal]
  2. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
    OASYS: a framework for analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1247-1266 [Journal]
  3. Richard W. Linderman, Paul C. Rossbach, David M. Gallagher
    Design and application of an optimizing XROM silicon compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1267-1275 [Journal]
  4. P. Sadayappan, V. Visvanathan
    Efficient sparse matrix factorization for circuit simulation on vector supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1276-1285 [Journal]
  5. Resve A. Saleh, A. Richard Newton
    The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1286-1298 [Journal]
  6. K. K. Low, Stephen W. Director
    An efficient methodology for building macromodels of IC fabrication processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1299-1313 [Journal]
  7. Charles H. Stapper
    Simulation of spatial fault distributions for integrated circuit yield estimations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1314-1318 [Journal]
  8. Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen
    Three-dimensional capacitance computations for VLSI/ULSI interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1319-1326 [Journal]
  9. Noriyoshi Itazaki, Kozo Kinoshita
    Test pattern generation for circuits with tri-state modules by Z-algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1327-1334 [Journal]
  10. Wayne Wei-Ming Dai
    Hierarchical placement and floorplanning in BEAR. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1335-1349 [Journal]
  11. Sabih H. Gerez, Otto E. Herrmann
    Switchbox routing by stepwise reshaping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1350-1361 [Journal]
  12. Raja Daoud, Füsun Özgüner
    Highly vectorizable fault simulation on the Cray X-MP supercomputer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1362-1365 [Journal]
  13. Lee-Sup Kim, Robert W. Dutton
    Modeling of the distributed gate RC effect in MOSFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1365-1367 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002