Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 5

1. Said Amellal, Bozena Kaminska
   Functional synthesis of digital systems with TASS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:537-552 [Journal]
   
2. Daniel Brand, Vijay S. Iyengar
   Identification of redundant delay faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:553-565 [Journal]
   
3. Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee
   A portable parallel algorithm for logic synthesis using transduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:566-580 [Journal]
   
4. P. N. Lam, Hon F. Li, S. C. Leung
   Optimization of state encoding in distributed circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:581-588 [Journal]
   
5. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Satisfaction of input and output encoding constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:589-602 [Journal]
   
6. C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh
   Optimal algorithms for bubble sort based non-Manhattan channel routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:603-609 [Journal]
   
7. Mitiko Miura-Mattausch
   Analytical MOSFET model for quarter micron technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:610-615 [Journal]
   
8. Kenny K. H. Toh, Andrew R. Neureuther, Edward W. Scheckler
   Algorithms for simulation of three-dimensional etching. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:616-624 [Journal]
   
9. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
   SWiTEST: a switch level test generation system for CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:625-637 [Journal]
   
10. Kuo-Feng Liao, Majid Sarrafzadeh
    Correction to "Boundary single-layer routing with movable terminals". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:638- [Journal]
    
11. Weiwei Mao, Michael D. Ciletti
    Reducing correlation to improve coverage of delay faults in scan-path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:638-646 [Journal]
    
12. Premachandran R. Menon, Hitesh Ahuja, Mohan Harihara
    Redundancy identification and removal in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:646-651 [Journal]
    
13. Michael Nicolaidis
    Fault secure property versus strongly code disjoint checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:651-658 [Journal]
    
14. Janusz A. Starzyk
    Hierarchical analysis of high frequency interconnect networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:658-664 [Journal]