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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 2

  1. Hyeong-Ju Kang, In-Cheol Park
    SAT-based unbounded symbolic model checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:129-140 [Journal]
  2. Le Cai, Yung-Hsiang Lu
    Energy management using buffer memory for streaming data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:141-152 [Journal]
  3. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:153-169 [Journal]
  4. Guoqing Chen, Eby G. Friedman
    An RLC interconnect model based on fourier analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:170-183 [Journal]
  5. Peng Li, Lawrence T. Pileggi
    Compact reduced-order modeling of weakly nonlinear analog and RF circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:184-203 [Journal]
  6. François Pêcheux, Christophe Lallement, Alain Vachoux
    VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:204-225 [Journal]
  7. Ting Mei, Jaijeet S. Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day
    Robust, stable time-domain methods for solving MPDEs of fast/slow systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:226-239 [Journal]
  8. Jiang Brandon Liu, Andreas G. Veneris
    Incremental fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:240-251 [Journal]
  9. Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
    A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:252-263 [Journal]
  10. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Optimized reseeding by seed ordering and encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:264-270 [Journal]
  11. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable reduction of interconnect circuits including self and mutual inductances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:271-277 [Journal]
  12. Yoonseo Choi, Taewhan Kim, Hwansoo Han
    Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:278-287 [Journal]
  13. Irith Pomeranz, Sudhakar M. Reddy
    On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:288-294 [Journal]
  14. A. Prasad Vinod, Edmund Ming-Kit Lai
    On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:295-304 [Journal]
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