Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 7

1. Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier
   Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:913-925 [Journal]
   
2. Cheng-Tsung Hwang, Yu-Chin Hsu
   Zone scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:926-934 [Journal]
   
3. Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
   Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:935-945 [Journal]
   
4. Stella N. Batalama, Dimitrios A. Pados, Theodore S. Papatheodorou
   A heuristic single-row router minimizing interstreet crossings. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:946-955 [Journal]
   
5. Stephen T. Frezza, Steven P. Levitan
   SPAR: a schematic place and route system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:956-973 [Journal]
   
6. Tai-Tsung Ho
   A density-based greedy router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:974-981 [Journal]
   
7. Mahesh S. Sharma, Narain D. Arora
   OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:982-987 [Journal]
   
8. Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas
   Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:988-996 [Journal]
   
9. Denis Martin, Nicholas C. Rumin
   Delay prediction from resistance-capacitance models of general MOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:997-1003 [Journal]
   
10. Lean Peterson, Sven Marrisson
    The design and implementation of a concurrent circuit simulation program for multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1004-1014 [Journal]
    
11. Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
    A transitive closure algorithm for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1015-1028 [Journal]
    
12. Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers
    Hierarchical test pattern generation: a cost model and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1029-1039 [Journal]
    
13. Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
    COMPACTEST: a method to generate compact test sets for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1040-1049 [Journal]
    
14. Irith Pomeranz, Sudhakar M. Reddy
    3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1050-1058 [Journal]
    
15. Kuo-En Chang
    Efficient algorithms of wiring channels with movable terminals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1059-1063 [Journal]
    
16. Lori E. Lucke, Keshab K. Parhi
    Data-flow transformations for critical path time reduction in high-level DSP synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1063-1068 [Journal]
    
17. Slawomir Pilarski, Tiko Kameda, André Ivanov
    Sequential faults and aliasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1068-1074 [Journal]