Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 8

1. Darko Kirovski, Milenko Drinic, Miodrag Potkonjak
   Engineering change protocols for behavioral and system synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1145-1155 [Journal]
   
2. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
   Weibull-based analytical waveform model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1156-1168 [Journal]
   
3. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
   Compressible area fill synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1169-1187 [Journal]
   
4. Bo Hu, Malgorzata Marek-Sadowska
   Multilevel fixed-point-addition-based VLSI placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1188-1203 [Journal]
   
5. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
   Power grid analysis using random walks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1204-1224 [Journal]
   
6. Xiaochun Duan, Kartikeya Mayaram
   An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1225-1233 [Journal]
   
7. Koji Ara, Kei Suzuki
   Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1234-1240 [Journal]
   
8. Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi
   Hierarchical approach to exact symbolic analysis of large analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1241-1250 [Journal]
   
9. Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince
   A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1250-1261 [Journal]
   
10. Hiren D. Patel, Sandeep K. Shukla
    Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1261-1271 [Journal]
    
11. Irith Pomeranz, Sudhakar M. Reddy
    On fault equivalence, fault dominance, and incompletely specified test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1271-1274 [Journal]
    
12. Jun Chen, Lei He
    Worst case crosstalk noise for nonswitching victims in high-speed buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1275-1283 [Journal]
    
13. Hao Yu, Lei He
    A provably passive and cost-efficient model for inductive interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1283-1294 [Journal]
    
14. Xiaoming Yu, Miron Abramovici
    Sequential circuit ATPG using combinational algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1294-1310 [Journal]