Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 9

1. Pinaki Mazumder, Jih-Shyr Yih
   Restructuring of square processor arrays by built-in self-repair circuit. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1255-1265 [Journal]
   
2. Catherine H. Gebotys, Mohamed I. Elmasry
   Global optimization approach for architectural synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1266-1278 [Journal]
   
3. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
   PLS: a scheduler for pipeline synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1279-1286 [Journal]
   
4. Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic
   Component synthesis from functional descriptions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1287-1299 [Journal]
   
5. D. I. Carson
   On O(p²) algorithms for planarization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1300-1302 [Journal]
   
6. Sy-Yen Kuo
   YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1303-1311 [Journal]
   
7. Sundarar Mohan, Pinaki Mazumder
   Wolverines: standard cell placement on a network of workstations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1312-1326 [Journal]
   
8. Antonio Abramo, Franco Venturi, Enrico Sangiorgi, Jack M. Higman, Bruno Riccò
   A numerical method to compute isotropic band models from anisotropic semiconductor band structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1327-1336 [Journal]
   
9. Shan-Ping Chin, Ching-Yuan Wu
   A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1337-1344 [Journal]
   
10. Edward W. Scheckler, Nelson N. Tam, Anton K. Pfau, Andrew R. Neureuther
    An efficient volume-removal algorithm for practical three-dimensional lithography simulation with experimental verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1345-1356 [Journal]
    
11. J. Will Specks, Walter L. Engl
    Computer-aided design and scaling of deep submicron CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1357-1367 [Journal]
    
12. David T. Zweidinger, Sang-Gug Lee, Robert M. Fox
    Compact modeling of BJT self-heating in SPICE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1368-1375 [Journal]
    
13. Valentino Liberali, V. F. Dias, M. Ciapponi, Franco Maloberti
    TOSCA: a simulator for switched-capacitor noise-shaping A/D converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1376-1386 [Journal]
    
14. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
    ILLIADS: a fast timing and reliability simulator for digital MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1387-1402 [Journal]
    
15. Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
    Fault simulation of parametric bridging faults in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1403-1410 [Journal]
    
16. Peter M. Maurer
    The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1411-1413 [Journal]
    
17. Ohyoung Song, Premachandran R. Menon
    Acceleration of trace-based fault simulation of combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1413-1419 [Journal]
    
18. Ohyoung Song, Premachandran R. Menon
    3-valued trace-based fault simulation of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1419-1424 [Journal]