Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 1

1. Robert P. Dick, Niraj K. Jha
   COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:2-16 [Journal]
   
2. Ingo Sander, Axel Jantsch
   System modeling and transformational design refinement in ForSyDe [formal system design]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:17-32 [Journal]
   
3. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
   Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
   
4. Jennifer L. Wong, Miodrag Potkonjak, Sujit Dey
   Optimizing designs using the addition of deflection operations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:50-59 [Journal]
   
5. Robert K. Thalhammer, Gerhard K. M. Wachutka
   Physically rigorous modeling of internal laser-probing techniques for microstructured semiconductor devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:60-70 [Journal]
   
6. Chris C. N. Chu, Evangeline F. Y. Young
   Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:71-79 [Journal]
   
7. Göran Jerke, Jens Lienig
   Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:80-90 [Journal]
   
8. Leendert M. Huisman
   Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:91-101 [Journal]
   
9. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
   Fast postplacement optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:102-118 [Journal]
   
10. Jennifer L. Wong, Gang Qu, Miodrag Potkonjak
    Optimization-intensive watermarking techniques for decision problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:119-127 [Journal]
    
11. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A library compatible driver output model for on-chip RLC transmission lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:128-136 [Journal]
    
12. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
    
13. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
    
14. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
    Nontree routing for reliability and yield improvement [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:148-156 [Journal]
    
15. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
    Coupling-aware high-level interconnect synthesis [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:157-164 [Journal]
    
16. Irith Pomeranz
    Constrained test generation for embedded synchronous sequential circuits with serial-input access. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:164-172 [Journal]