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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1983, volume: 2, number: 2

  1. Dwight D. Hill
    Edisim: A Graphical Simulator Interface for LSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:57-61 [Journal]
  2. Yuh-Zen Liao, Chak-Kuen Wong
    An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:62-69 [Journal]
  3. T. Watanabe, Makoto Endo, N. Miyahara
    A New Automatic Logic Interconnection Verification System for VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:70-82 [Journal]
  4. Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
    A Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:82-94 [Journal]
  5. Donald E. Thomas, G. W. Leive
    Automating Technology Relative Logic Synthesis and Module Selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:94-105 [Journal]
  6. D. B. Estreich
    A Simulation Model for Schottky Diodes in GaAs Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:106-111 [Journal]
  7. Richard C. Jaeger, Fritz H. Gaensslen, Sherra E. Diehl
    An Efficient Numerical Algorithm for Simulation of MOS Capacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:111-116 [Journal]
  8. Chet A. Palesko, Lex A. Akers
    Logic Partitioning for Minimizing Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:117-121 [Journal]
  9. T. Shima, H. Tamada, Ryo Luong, Mo Dang
    Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:121-126 [Journal]
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