Dwight D. Hill Edisim: A Graphical Simulator Interface for LSI Design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:57-61 [Journal]
Yuh-Zen Liao, Chak-Kuen Wong An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:62-69 [Journal]
T. Watanabe, Makoto Endo, N. Miyahara A New Automatic Logic Interconnection Verification System for VLSI Design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:70-82 [Journal]
Donald E. Thomas, G. W. Leive Automating Technology Relative Logic Synthesis and Module Selection. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:94-105 [Journal]
D. B. Estreich A Simulation Model for Schottky Diodes in GaAs Integrated Circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:106-111 [Journal]
T. Shima, H. Tamada, Ryo Luong, Mo Dang Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:121-126 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP