Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 5

1. Vasco M. Manquinho, João P. Marques Silva
   Search pruning techniques in SAT-based branch-and-bound algorithmsfor the binate covering problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:505-516 [Journal]
   
2. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
   Efficient synthesis of OTA network for linear analog functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:517-533 [Journal]
   
3. Wim Schoenmaker, Peter Meuris
   Electromagnetic interconnects and passives modeling: softwareimplementation issues. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:534-543 [Journal]
   
4. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
   Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:544-553 [Journal]
   
5. Amir H. Salek, Jinan Lou, Massoud Pedram
   Hierarchical buffered routing tree generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:554-567 [Journal]
   
6. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
   Fast and exact transistor sizing based on iterative relaxation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:568-581 [Journal]
   
7. Reinaldo A. Bergamaschi
   Bridging the domains of high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:582-596 [Journal]
   
8. Anshuman Chandra, Krishnendu Chakrabarty
   Low-power scan testing and test data compression forsystem-on-a-chip. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:597-604 [Journal]
   
9. Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
   TETA: transistor-level waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:605-616 [Journal]
   
10. Der-Cheng Huang, Wen-Ben Jone
    A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:617-628 [Journal]
    
11. Irith Pomeranz, Sudhakar M. Reddy
    Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:628-637 [Journal]