Vasco M. Manquinho, João P. Marques Silva Search pruning techniques in SAT-based branch-and-bound algorithmsfor the binate covering problem. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:505-516 [Journal]
Reinaldo A. Bergamaschi Bridging the domains of high-level and logic synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:582-596 [Journal]
Der-Cheng Huang, Wen-Ben Jone A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:617-628 [Journal]
Irith Pomeranz, Sudhakar M. Reddy Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:628-637 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP