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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 7

  1. Ingmar Neumann, Wolfgang Kunz
    Layout driven retiming using the coupled edge timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:825-835 [Journal]
  2. Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
    Optimal joint module-selection and retiming with carry-save representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:836-846 [Journal]
  3. Vishnu Swaminathan, Krishnendu Chakrabarty
    Energy-conscious, deterministic I/O device scheduling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:847-858 [Journal]
  4. Sarnath Ramnath
    New approximations for the rectilinear Steiner arborescence problem [VLSI layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:859-869 [Journal]
  5. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Min-cost flow-based algorithm for simultaneous pin assignment and routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:870-878 [Journal]
  6. Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr
    On smoothing three-dimensional Monte Carlo ion implantation simulation results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:879-883 [Journal]
  7. Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
    INDUCTWISE: inductance-wise interconnect simulator and extractor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:884-894 [Journal]
  8. Xiaoling Huang, Chris S. Gathercole, H. Alan Mantooth
    Modeling nonlinear dynamics in analog circuits via root localization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:895-907 [Journal]
  9. Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
    Data dependency size estimation for use in memory optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:908-921 [Journal]
  10. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Fault equivalence identification in combinational circuits using implication and evaluation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:922-936 [Journal]
  11. Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    On the skew-bounded minimum-buffer routing tree problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:937-945 [Journal]
  12. Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska
    A new reasoning scheme for efficient redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:945-951 [Journal]
  13. Wai-Kei Mak, Evangeline F. Y. Young
    Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:952-959 [Journal]
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