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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 5

  1. C. Leonard Berman, Louise Trevillyan
    Global flow optimization in automatic logic design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:557-564 [Journal]
  2. Genhong Ruan, Jiri Vlach, James A. Barby, Ajoy Opal
    Analog functional simulator for multilevel systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:565-576 [Journal]
  3. Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici
    An accurate analytical delay model for BiCMOS driver circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:577-588 [Journal]
  4. Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin
    A recursive technique for computing delays in series-parallel MOS transistor circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:589-595 [Journal]
  5. Wayne Bower, Carl Seaquist, Wayne Wolf
    A framework for industrial layout generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:596-603 [Journal]
  6. Krishna P. Belkhale, Prithviraj Banerjee
    Parallel algorithms for VLSI circuit extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:604-618 [Journal]
  7. Shinji Odanaka, Akira Hiroki, Kikuyo Ohe, Kaori Moriyama, Hiroyuki Umimoto
    SMART-II: a three-dimensional CAD model for submicrometer MOSFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:619-628 [Journal]
  8. Hong June Park, Ping Keung Ko, Chenming Hu
    A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:629-642 [Journal]
  9. Richard B. Fair, Carl L. Gardner, Michael J. Johnson, Stephen W. Kenkel, Donald J. Rose, J. E. Rose, Ravi Subrahmanyan
    Two-dimensional process simulation using verified phenomenological models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:643-651 [Journal]
  10. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Test generation and verification for highly sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:652-667 [Journal]
  11. Giuseppe Acciani, D. Congedo, Bruno Dilecce
    Improving the computational efficiency of the tree relaxation method for an iterative solution of linear circuit equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:668-670 [Journal]
  12. H. Y. Chen, Sung-Mo Kang
    A new circuit optimization technique for high performance CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:670-677 [Journal]
  13. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    Fault simulation of unconventional faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:677-682 [Journal]
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