Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 10

1. Ali Dasdan, Rajesh K. Gupta
   Faster maximum and minimum mean cycle algorithms for system-performance analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:889-899 [Journal]
   
2. Bharat P. Dave, Niraj K. Jha
   COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:900-919 [Journal]
   
3. Robert P. Dick, Niraj K. Jha
   MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:920-935 [Journal]
   
4. Miodrag Potkonjak, Mani B. Srivastava
   Behavioral optimization using the manipulation of timing constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:936-947 [Journal]
   
5. Luca Benini, Patrick Vuillod, Giovanni De Micheli
   Iterative remapping for logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:948-964 [Journal]
   
6. Rolf Drechsler, Bernd Becker
   Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:965-973 [Journal]
   
7. Taewhan Kim, William Jao, Steven W. K. Tjiang
   Circuit optimization using carry-save-adder cells. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:974-984 [Journal]
   
8. Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
   Characterization and parameterized generation of synthetic combinational benchmark circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:985-996 [Journal]
   
9. Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
   Full-wave analysis of high-speed interconnects using complex frequency hopping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:997-1016 [Journal]
   
10. Irith Pomeranz, Sudhakar M. Reddy
    Test sequences to achieve high defect coverage for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1017-1029 [Journal]
    
11. Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
    A graph representation for programmable logic arrays to facilitate testing and logic design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1030-1043 [Journal]
    
12. Krishnendu Chakrabarty, Brian T. Murray
    Design of built-in test generator circuits using width compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1044-1051 [Journal]
    
13. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1051-1060 [Journal]