Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 12

1. Edward A. Lee, Alberto L. Sangiovanni-Vincentelli
   A framework for comparing models of computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1217-1229 [Journal]
   
2. Carl J. Wordelman, Thomas J. T. Kwan, Charles M. Snell
   Comparison of statistical enhancement methods for Monte Carlo semiconductor simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1230-1235 [Journal]
   
3. Walter Bohmayr, Alexander Burenkov, Jürgen Lorenz, Heiner Ryssel, Siegfried Selberherr
   Monte Carlo simulation of silicon amorphization during ion implantation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1236-1243 [Journal]
   
4. Richard Plasun, Michael Stockinger, Siegfried Selberherr
   Integrated optimization capabilities in the VISTA technology CAD framework. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1244-1251 [Journal]
   
5. M. B. Anand, Hideki Shibata, Masakazu Kakumu
   Multiobjective optimization of VLSI interconnect parameters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1252-1261 [Journal]
   
6. Akira Nagao, Isao Shirakawa, Takashi Kambe
   A layout approach to monolithic microwave IC. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1262-1272 [Journal]
   
7. Aurobindo Dasgupta, Ramesh Karri
   High-reliability, low-energy microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1273-1280 [Journal]
   
8. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
   Low-power state assignment targeting two- and multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1281-1291 [Journal]
   
9. Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu
   JiffyTune: circuit optimization using time-domain sensitivities. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1292-1309 [Journal]
   
10. Jacob Savir
    Random pattern testability of memory address logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1310-1318 [Journal]
    
11. Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien
    Retiming DAGs [direct acyclic graph]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1319-1325 [Journal]
    
12. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for minimizing power dissipation in scan and combinational circuits during test application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1325-1333 [Journal]
    
13. Aiguo Xie, Peter A. Beerel
    Efficient state classification of finite-state Markov chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1334-1339 [Journal]