Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 9

1. Arun Achyuthan, Mohamed I. Elmasry
   Mixed analog/digital hardware synthesis of artificial neural networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1073-1087 [Journal]
   
2. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
   Spectral K-way ratio-cut partitioning and clustering. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1088-1096 [Journal]
   
3. Brian Lockyear, Carl Ebeling
   Optimal retiming of level-clocked circuits using symmetric clock schedules. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1097-1109 [Journal]
   
4. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
   Power efficient technology decomposition and mapping under an extended power consumption model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1110-1122 [Journal]
   
5. Farid N. Najm
   Low-pass filter for computing the transition density in digital circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1123-1131 [Journal]
   
6. Sherif H. K. Embabi, R. Damodaran
   Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1132-1142 [Journal]
   
7. Wolfgang Kunz, Dhiraj K. Pradhan
   Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1143-1158 [Journal]
   
8. Tai-Yu Chou, Zoltan J. Cendes
   Capacitance calculation of IC packages using the finite element method and planes of symmetry. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1159-1166 [Journal]
   
9. Sudhir M. Gowda, Bing J. Sheu
   BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1166-1170 [Journal]
   
10. Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas
    A method for pseudo-exhaustive test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1170-1178 [Journal]
    
11. Ted Stanion, Carl Sechen
    Boolean division and factorization using binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1179-1184 [Journal]