Brian Lockyear, Carl Ebeling Optimal retiming of level-clocked circuits using symmetric clock schedules. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1097-1109 [Journal]

Farid N. Najm Low-pass filter for computing the transition density in digital circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1123-1131 [Journal]

Sherif H. K. Embabi, R. Damodaran Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1132-1142 [Journal]

Wolfgang Kunz, Dhiraj K. Pradhan Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1143-1158 [Journal]

Tai-Yu Chou, Zoltan J. Cendes Capacitance calculation of IC packages using the finite element method and planes of symmetry. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1159-1166 [Journal]

Sudhir M. Gowda, Bing J. Sheu BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1166-1170 [Journal]

Ted Stanion, Carl Sechen Boolean division and factorization using binary decision diagrams. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1179-1184 [Journal]

NOTICE1

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NOTICE2

The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP