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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 6

  1. Jan M. Rabaey, Miodrag Potkonjak
    Estimating implementation bounds for real time DSP application specific circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:669-683 [Journal]
  2. Tae Won Cho, Sam S. Pyo, J. Robert Heath
    PARALLEX: a parallel approach to switchbox routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:684-693 [Journal]
  3. Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
    Block placement with a Boltzmann Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:694-701 [Journal]
  4. Y. Apanovich, Eugeny D. Lyumkis, Boris S. Polsky, Alex I. Shur, Peter A. Blakey
    Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:702-711 [Journal]
  5. Udaya A. Ranawake, Carl Huster, Patrick M. Lenders, Stephen Marshall Goodnick
    PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:712-724 [Journal]
  6. Jason Yao-Tsung Tsai, Kuo-Don Hong, Yin-Lun Yuan
    An efficient analytical model for calculating trapped charge in amorphous silicon. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:725-728 [Journal]
  7. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
    Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:729-736 [Journal]
  8. Sina Balkir, Mehmet Yanilmaz, Martin A. Plonus
    Numerical integration using Bezier splines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:737-745 [Journal]
  9. Anirudh Devgan, Ronald A. Rohrer
    Adaptively controlled explicit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:746-762 [Journal]
  10. Curtis L. Ratzlaff, Lawrence T. Pillage
    RICE: rapid interconnect circuit evaluation using AWE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:763-776 [Journal]
  11. Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab
    Structural and behavioral synthesis for testability techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:777-785 [Journal]
  12. Silvano Gai, Pier Luca Montessoro
    Creator: new advanced concepts in concurrent simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:786-795 [Journal]
  13. Linda S. Milor, Alberto L. Sangiovanni-Vincentelli
    Minimizing production test time to detect faults in analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:796-813 [Journal]
  14. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:814-822 [Journal]
  15. Hsu-Chun Yen
    On multiterminal single bend wirability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:822-826 [Journal]
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