Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 11

1. Peter Marwedel
   Guest editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1281-1282 [Journal]
   
2. Andrea Acquaviva, Luca Benini, Bruno Riccò
   Software-controlled processor speed setting for low-power streamingmultimedia. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1283-1292 [Journal]
   
3. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
   Automatic generation and targeting of application-specificoperating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1293-1301 [Journal]
   
4. Jens Wagner, Rainer Leupers
   C compiler design for a network processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1302-1308 [Journal]
   
5. Peter Petrov, Alex Orailoglu
   Performance and power effectiveness in embedded processors customizable partitioned caches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1309-1318 [Journal]
   
6. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
   A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]
   
7. Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan
   Analysis of the influence of register file size on energyconsumption, code size, and execution time. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1329-1337 [Journal]
   
8. Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
   A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1338-1354 [Journal]
   
9. Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
   Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1355-1371 [Journal]