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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 3

  1. Shen-Chuan Tai, M. W. Du, Richard C. T. Lee
    A transformational approach to synthesizing combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:286-295 [Journal]
  2. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Optimum and heuristic algorithms for an approach to finite state machine decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:296-310 [Journal]
  3. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Irredundant interacting sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:311-325 [Journal]
  4. Seung Ho Hwang, A. Richard Newton
    An efficient verifier for finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:326-334 [Journal]
  5. Per Andersson
    Design representation in Movie. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:335-345 [Journal]
  6. Dan Adler
    Switch-level simulation using dynamic graph algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:346-355 [Journal]
  7. Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt Antreich
    GORDIAN: VLSI placement by quadratic programming and slicing optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:356-365 [Journal]
  8. Mehmet Yanilmaz, Virgil Eveleigh
    Numerical device modeling for electronic circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:366-375 [Journal]
  9. Hong June Park, Ping Keung Ko, Chenming Hu
    A charge sheet capacitance model of short channel MOSFETs for SPICE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:376-389 [Journal]
  10. Sarma Sastry, Amitava Majumdar
    Test efficiency analysis of random self-test of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:390-398 [Journal]
  11. Charles H. Stapper
    Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:399-406 [Journal]
  12. Konstantinos I. Diamantaras, Niraj K. Jha
    A new transition count method for testing of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:407-410 [Journal]
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