Journals in DBLP
Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond Kirkpatrick Repeater scaling and its impact on CAD. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:451-463 [Journal ] Andrew B. Kahng , Xu Xu Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:464-471 [Journal ] Saurabh N. Adya , Mehmet Can Yildiz , Igor L. Markov , Paul Villarrubia , Phiroze N. Parakh , Patrick H. Madden Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal ] Murat R. Becer , Ravi Vaidyanathan , Chanhee Oh , Rajendran Panda Crosstalk noise control in an SoC physical design flow. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:488-497 [Journal ] Masanori Hashimoto , Yuji Yamada , Hidetoshi Onodera Equivalent waveform propagation for static timing analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:498-508 [Journal ] Chandramouli V. Kashyap , Charles J. Alpert , Frank Liu , Anirudh Devgan Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:509-516 [Journal ] Charles J. Alpert , Gopal Gandham , Milos Hrkic , Jiang Hu , Stephen T. Quay , Cliff C. N. Sze Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal ] Bo Hu , Malgorzata Marek-Sadowska Fine granularity clustering-based placement. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:527-536 [Journal ] Chin-Chih Chang , Jason Cong , Michail Romesis , Min Xie Optimality and scalability study of existing placement algorithms. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:537-549 [Journal ] Jason Cong , Yiping Fan , Guoling Han , Xun Yang , Zhiru Zhang Architecture and synthesis for on-chip multicycle communication. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:550-564 [Journal ] Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:565-572 [Journal ] Yan Feng , Dinesh P. Mehta , Hannah Honghua Yang Constrained floorplanning using network flows. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:572-580 [Journal ] Robert K. Thalhammer , Gerhard K. M. Wachutka Corrections to "Physically Rigorous Modeling of Internal Laser-Probing Techniques for Microstructured Semiconductor Devices". [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:581-582 [Journal ]