Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 6

1. Pak K. Chan, Martine D. F. Schlag
   Bounds on signal delay in RC mesh networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:581-589 [Journal]
   
2. Mahesh Sharma, Graham F. Carey
   Semiconductor device simulation using adaptive refinement and flux upwinding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:590-598 [Journal]
   
3. Hiroyuki Umimoto, Shinji Odanaka, Ichiro Nakao, Hideya Esaki
   Numerical modeling of nonplanar oxidation coupled with stress effects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:599-607 [Journal]
   
4. Guang-Wen Pan, Kenneth S. Olson, Barry K. Gilbert
   Improved algorithmic methods for the prediction of wavefront propagation behavior in multiconductor transmission lines for high frequency digital signal processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:608-621 [Journal]
   
5. Shoichiro Yamada, Hirokai Okude, Tamotsu Kasai
   A hierarchical algorithm for one-dimensional gate assignment based on contraction of nets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:622-629 [Journal]
   
6. S. Chowdhury
   Analytical approaches to the combinatorial optimization in linear placement problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:630-639 [Journal]
   
7. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
   Time-efficient VLSI artwork analysis algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:640-648 [Journal]
   
8. Toshiaki Tanaka, Tsutomu Kobayashi, Osamu Karatsu
   HARP: FORTRAN to silicon [compilation system]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:649-660 [Journal]
   
9. Pierre G. Paulin, John P. Knight
   Force-directed scheduling for the behavioral synthesis of ASICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:661-679 [Journal]
   
10. Fathey M. El-Turky, Elizabeth E. Perry
    BLADES: an artificial intelligence approach to analog circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:680-692 [Journal]
    
11. Per Andersson, Lars H. Philipson
    Movie-an interactive environment for silicon compilation tools. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:693-701 [Journal]
    
12. Maciej J. Ciesielski
    Layer assignment for VLSI interconnect delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:702-707 [Journal]