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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 1

  1. Jason Cong, Yuzheng Ding
    FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:1-12 [Journal]
  2. Martine D. F. Schlag, Jackson Kong, Pak K. Chan
    Routability-driven technology mapping for lookup table-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:13-26 [Journal]
  3. Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran
    On the intrinsic Rent parameter and spectra-based partitioning methodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:27-37 [Journal]
  4. Majid Sarrafzadeh, Kuo-Feng Liao, Chak-Kuen Wong
    Single-layer global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:38-47 [Journal]
  5. Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto
    QFP wiring problem-introduction and analytical considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:48-56 [Journal]
  6. Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser
    Circuit analysis and optimization driven by worst-case distances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:57-71 [Journal]
  7. Franz Fasching, Walter Tuppa, Siegfried Selberherr
    VISTA-the data level. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:72-81 [Journal]
  8. Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong
    Semiconductor wafer representation for TCAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:82-95 [Journal]
  9. Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
    Algorithms for the transient simulation of lossy interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:96-104 [Journal]
  10. W. W. Wong, Juin J. Liou
    JFET circuit simulation using SPICE implemented with an improved model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:105-109 [Journal]
  11. So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
    A multi-probe approach for MCM substrate testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:110-121 [Journal]
  12. Filip Van Aelten, Jonathan Allen, Srinivas Devadas
    Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:122-134 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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