Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 8

1. Andrea Casotto, Alberto L. Sangiovanni-Vincentelli
   Automated design management using traces. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1077-1095 [Journal]
   
2. Per Andersson, Lars H. Philipson
   Interaction semantics of a symbolic layout editor for parameterized modules. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1096-1106 [Journal]
   
3. John A. Nestor, Ganesh Krishnamoorthy
   SALSA: a new approach to scheduling with timing constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1107-1122 [Journal]
   
4. Irith Pomeranz, Kwang-Ting Cheng
   STOIC: state assignment based on output/input functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1123-1131 [Journal]
   
5. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
   Synchronization of pipelines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1132-1146 [Journal]
   
6. Wing Ning Li, Andrew Lim, Prathima Agrawal, Sartaj Sahni
   On the circuit implementation problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1147-1156 [Journal]
   
7. Jason Cong, Andrew B. Kahng, Gabriel Robins
   Matching-based methods for high-performance clock routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1157-1169 [Journal]
   
8. Denis Deschacht, Michel Robert, Nadine Azemard-Crestani, Daniel Auvergne
   Post-layout timing simulation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1170-1177 [Journal]
   
9. Jack A. Feldman, Israel A. Wagner, Shmuel Wimer
   An efficient algorithm for some multirow layout problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1178-1185 [Journal]
   
10. Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli
    Area routing for analog layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1186-1197 [Journal]
    
11. D. Sreenivasa Rao, Fadi J. Kurdahi
    On clustering for maximal regularity extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1198-1208 [Journal]
    
12. Chih-Chuan Lin, Mark E. Law, Rex E. Lowther
    Automatic grid refinement and higher order flux discretization for diffusion modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1209-1216 [Journal]
    
13. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Delay-fault test generation and synthesis for testability under a standard scan design methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1217-1231 [Journal]
    
14. Jacob Savir, Srinivas Patil
    Scan-based transition test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1232-1241 [Journal]
    
15. M. A. Styblinski, Min Huang
    Drift reliability optimization in IC design: generalized formulation and practical examples. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1242-1252 [Journal]