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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 7

  1. Kris Tiri, Ingrid Verbauwhede
    A digital design flow for secure integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1197-1208 [Journal]
  2. Laura Pozzi, Kubilay Atasu, Paolo Ienne
    Exact and approximate algorithms for the extension of embedded processor instruction sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1209-1229 [Journal]
  3. Christopher Umans, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli
    Complexity of two-level logic minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1230-1246 [Journal]
  4. Jongsun Park, Khurram Muhammad, Kaushik Roy
    Efficient modeling of 1/falpha/ noise using multirate process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1247-1256 [Journal]
  5. Guoyong Shi, Bo Hu, C.-J. Richard Shi
    On symbolic model order reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1257-1272 [Journal]
  6. Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw
    Statistical interconnect metrics for physical-design optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1273-1288 [Journal]
  7. Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
    Profile-guided microarchitectural floor planning for deep submicron processor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1289-1300 [Journal]
  8. Andrew B. Kahng, Sherief Reda
    Wirelength minimization for min-cut placements via placement feedback. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1301-1312 [Journal]
  9. Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov
    Min-cut floorplacement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1313-1326 [Journal]
  10. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
    A statistical methodology for wire-length prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1327-1336 [Journal]
  11. Peng Rong, Massoud Pedram
    Battery-aware power management based on Markovian decision processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1337-1349 [Journal]
  12. Munkang Choi, Linda S. Milor
    Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1350-1367 [Journal]
  13. S. Banerjee, D. Mukhopadhyay, C. V. G. Rao, D. R. Chowdhury
    An integrated DFT solution for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1368-1377 [Journal]
  14. L. Knockaert, T. Dhaene
    Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1377-1381 [Journal]
  15. Knockaert Radecka, Zeljko Zilic
    Arithmetic transforms for compositions of sequential and imprecise datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1382-1391 [Journal]
  16. C.-J. Richard Shi, Michael W. Tian, Guoyong Shi
    Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1392-1400 [Journal]
  17. Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen
    Analytical model for crosstalk and intersymbol interference in point-to-point buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1400-1410 [Journal]
  18. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
    Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1411-1418 [Journal]
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