Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 11

1. Shinobu Nagayama, Tsutomu Sasao
   On the optimization of heterogeneous MDDs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1645-1659 [Journal]
   
2. Federico Angiolini, Luca Benini, Alberto Caprara
   An efficient profile-based algorithm for scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1660-1676 [Journal]
   
3. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
   Input space-adaptive optimization for embedded-software synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1677-1693 [Journal]
   
4. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Generation of distributed logic-memory architectures through high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1694-1711 [Journal]
   
5. Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
   Power modeling and characteristics of field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1712-1724 [Journal]
   
6. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
   Modeling delay and noise in arbitrarily coupled RC trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1725-1739 [Journal]
   
7. Bo Yang, Ramesh Karri, David A. McGrew
   Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1740-1747 [Journal]
   
8. Chien-Mo James Li, Edward J. McCluskey
   Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1748-1759 [Journal]
   
9. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
   Nonlinear decision boundaries for testing analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1760-1773 [Journal]
   
10. Mehdi Baradaran Tahoori, Subhasish Mitra
    Application-independent testing of FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1774-1783 [Journal]
    
11. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
    Probability distribution of signal arrival times using Bayesian networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1784-1794 [Journal]
    
12. Ken Tseng, Mark Horowitz
    False coupling exploration in timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1795-1805 [Journal]