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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 4

  1. Scott H. Goodwin-Johansson, Ravi Subrahmanyan, Carey E. Floyd, Hisham Z. Massoud
    Two-dimensional impurity profiling with emission computed tomography techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:323-335 [Journal]
  2. Brian J. Mulvaney, Walter B. Richardson, Timothy L. Crandle
    PEPPER-a process simulator for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:336-349 [Journal]
  3. Robert Anholt, Thomas W. Sigmon
    A process and device model for GaAs MESFET technology: GATES. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:350-359 [Journal]
  4. Franco Venturi, R. Kent Smith, Enrico Sangiorgi, Mark R. Pinto, Bruno Riccò
    A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:360-369 [Journal]
  5. Chang G. Hwang, Robert W. Dutton
    Improved physical modeling of submicron MOSFETs based on parameter extraction using 2-D simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:370-379 [Journal]
  6. William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse
    Extracting transistor changes from device simulations by gradient fitting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:380-394 [Journal]
  7. Walter R. Curtice
    Intrinsic GaAs MESFET equivalent circuit models generated from two-dimensional simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:395-402 [Journal]
  8. Chang-Sheng Ying, Joshua Sook-Leung Wong
    An analytical approach to floorplanning for hierarchical building blocks layout [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:403-412 [Journal]
  9. Mandalagiri S. Chandrasekhar, Melvin A. Breuer
    Optimal routing of two rectangular blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:413-430 [Journal]
  10. Baher Haroun, Mohamed I. Elmasry
    Architectural synthesis for DSP silicon compilers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:431-447 [Journal]
  11. David N. Deutsch
    Two new and 'more difficult' channel routing problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:448- [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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