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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 9

  1. James C. Hoe, Arvind
    Operation-centric hardware description and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1277-1288 [Journal]
  2. Lei Li, Krishnendu Chakrabarty
    Test set embedding for deterministic BIST using a reconfigurable interconnection network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1289-1305 [Journal]
  3. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Ring generators - new devices for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1306-1320 [Journal]
  4. Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim
    A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1321-1337 [Journal]
  5. Hai Zhou, Chuan Lin
    Retiming for wire pipelining in system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1338-1345 [Journal]
  6. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A simple metric for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1346-1354 [Journal]
  7. Xiaoliang Bai, Sujit Dey
    High-level crosstalk defect Simulation methodology for system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1355-1361 [Journal]
  8. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    IDAP: a tool for high-level power estimation of custom array structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1361-1369 [Journal]
  9. Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
    A unified approach to variable voltage scheduling for nonideal DVS processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1370-1377 [Journal]
  10. Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo
    Probabilistic crosstalk delay estimation for ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1377-1383 [Journal]
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