Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 10

1. Peng Li, Lawrence T. Pileggi
   Efficient per-nonlinearity distortion analysis for analog and RF circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1297-1309 [Journal]
   
2. Valentina Ciriani
   Synthesis of SPP three-level logic networks using affine spaces. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1310-1323 [Journal]
   
3. Mohab Anis, Shawki Areibi, Mohamed I. Elmasry
   Design and optimization of multithreshold CMOS (MTCMOS) circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1324-1342 [Journal]
   
4. Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
   Effective free space management for cut-based placement via analytical constraint generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1343-1353 [Journal]
   
5. Zion Cien Shen, Chris C. N. Chu
   Bounds on the number of slicing, mosaic, and general floorplans. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1354-1361 [Journal]
   
6. Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang
   ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1362-1370 [Journal]
   
7. Zaid Al-Ars, A. J. van de Goor
   Test generation and optimization for DRAM cell defects using electrical simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1371-1384 [Journal]
   
8. Junwei Hou, Abhijit Chatterjee
   Concurrent transient fault simulation for analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1385-1398 [Journal]
   
9. Saravanan Padmanaban, Spyros Tragoudas
   An implicit path-delay fault diagnosis methodology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1399-1408 [Journal]
   
10. Jeongjin Roh, Jacob A. Abraham
    A comprehensive signature analysis scheme for oscillation-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1409-1423 [Journal]
    
11. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1424-1431 [Journal]
    
12. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Wordlength optimization for linear digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1432-1442 [Journal]
    
13. Michael Dimopoulos, Panagiotis Linardis
    Accelerating the compaction of test sequences in sequential circuits through problem size reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1443-1449 [Journal]
    
14. Irith Pomeranz, Sudhakar M. Reddy
    Test data compression based on input-output dependence. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1450-1455 [Journal]