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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 8

  1. Weiping Shi, Fangqing Yu
    A divide-and-conquer algorithm for 3-D capacitance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1157-1163 [Journal]
  2. Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
    Transition reduction in memory buses using sector-based encoding techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1164-1174 [Journal]
  3. Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha
    Register binding-based RTL power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1175-1183 [Journal]
  4. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay-budget assignment on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1184-1199 [Journal]
  5. Qing Huo Liu, Candong Cheng, Hisham Z. Massoud
    The spectral grid method: a novel fast Schrodinger-equation solver for semiconductor nanodevice simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1200-1208 [Journal]
  6. Loc Vu-Quoc, Yuhu Zhai, Khai D. T. Ngo
    Efficient simulation of coupled circuit-field problems: generalized Falk method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1209-1219 [Journal]
  7. Ketan N. Patel, John P. Hayes, Igor L. Markov
    Fault testing for reversible circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1220-1230 [Journal]
  8. Aseem Agarwal, Vladimir Zolotov, David Blaauw
    Statistical clock skew analysis considering intradie-process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1231-1242 [Journal]
  9. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Logic of constraints: a quantitative performance and functional constraint formalism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1243-1255 [Journal]
  10. Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas
    Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1256-1263 [Journal]
  11. Yehea I. Ismail, Chirayu S. Amin
    Computation of signal-threshold crossing times directly from higher order moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1264-1276 [Journal]
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