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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1987, volume: 6, number: 3

  1. Masaharu Hirayama
    A Silicon Compiler System Based on Asynchronous Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:297-304 [Journal]
  2. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
    High-Speed Logic Simulation on Vector Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:305-321 [Journal]
  3. Yukihiro Nakamura
    An Integrated Logic Design Environment Based on Behavioral Description. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:322-336 [Journal]
  4. Takashi Mitsuhashi, Kenji Yoshida
    A Resistance Calculation Algorithm and Its Application to Circuit Extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:337-345 [Journal]
  5. M. Terai, Y. Ajioka, T. Noda, M. Ozaki, T. Umeki, K. Sato
    Symbolic Layout System: Application Results and Functional Improvements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:346-354 [Journal]
  6. Gotaro Odawara, Takahisa Hiraide, Osamu Nishina
    Partitioning and Placement Technique for CMOS Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:355-363 [Journal]
  7. Atsushi Kurosawa, Kazutaka Yamada, Aritoyo Kishimoto, Kunio Mori, Nobuyuki Nishiguchi
    A Practical CAD System Application for Full Custom VLSI Microcomputer Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:364-373 [Journal]
  8. Masaki Ishikawa, T. Matsuda, T. Yoshimura, Satoshi Goto
    Compaction-Based Custom LSI Layout Design Method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:374-382 [Journal]
  9. Masahiro Fukui, A. Yamamoto, R. Yamaguchi, Sigeru Hayama, Y. Mano
    A Block Interconnection Algorithm for Hierarchical Layout System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:383-391 [Journal]
  10. Takao Nishida, Shunsuke Miyamoto, Tokinori Kozawa, Katsuya Satoh
    RFSIM: Reduced Fault Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:392-402 [Journal]
  11. Yoshihiko Hirai, Masaru Sasago, Masayuki Endo, K. Tsuji, Yojiro Mano
    Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:403-409 [Journal]
  12. S. Isomae, S. Yamamoto
    A New Two-Dimensional Silicon Oxidation Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:410-416 [Journal]
  13. S. Yamamoto, T. Kure, M. Ohgo, Teruo Matsuzawa, S. Tachi, H. Sunami
    A Two-Dimensional Etching Profile Simulator: ESPRIT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:417-422 [Journal]
  14. Y. Ohkura, Toru Toyabe, H. Masuda
    Analysis of MOSFET Capacitances and Their Behavior at Short-Channel Lengths Using an AC Device Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:423-430 [Journal]
  15. A. Moniwa, Teruo Matsuzawa, T. Ito, H. Sunami
    A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:431-438 [Journal]
  16. M. Ohgo, Y. Takano, A. Moniwa, S. Yamamoto, Y. Sakai, H. Masuda, H. Sunami
    A Two-Dimensional Integrated Process Simulator: SPIRIT-I. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:439-445 [Journal]
  17. Teruo Matsuzawa, A. Moniwa, N. Hasegawa, H. Sunami
    Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:446-451 [Journal]
  18. Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato
    A New Design-Centering Methodology for VLSI Device Development. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:452-461 [Journal]
  19. Yoichi Shiraishi, Jun'ya Sakemi
    A Permeation Router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:462-471 [Journal]
  20. Rakesh Chadha, Kishore Singhal, Jiri Vlach, Ernst Christen, Milan Vlach
    WATOPT -- An Optimizer for Circuit Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:472-479 [Journal]
  21. Norman P. Jouppi
    Derivation of Signal Flow Direction in MOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:480-490 [Journal]
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