Jovanka Ciric, Carl Sechen Efficient canonical form for Boolean matching of complex functions in large libraries. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:535-544 [Journal]
Srini Krishnamoorthy, Russell Tessier Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:545-559 [Journal]
Jae-Gon Kim, Yeong-Dae Kim A linear programming-based algorithm for floorplanning in VLSI design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:584-592 [Journal]
Chunsheng Liu, Krishnendu Chakrabarty Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:593-604 [Journal]
Louis Scheffer Some conditions under which hierarchical verification is O(N). [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:643-646 [Journal]
Cliff C. N. Sze, Ting-Chi Wang Optimal circuit clustering for delay minimization under a more general delay model. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:646-651 [Journal]