Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 5

1. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
   Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:517-534 [Journal]
   
2. Jovanka Ciric, Carl Sechen
   Efficient canonical form for Boolean matching of complex functions in large libraries. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:535-544 [Journal]
   
3. Srini Krishnamoorthy, Russell Tessier
   Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:545-559 [Journal]
   
4. Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
   Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:560-572 [Journal]
   
5. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
   A practical methodology for early buffer and wire resource allocation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:573-583 [Journal]
   
6. Jae-Gon Kim, Yeong-Dae Kim
   A linear programming-based algorithm for floorplanning in VLSI design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:584-592 [Journal]
   
7. Chunsheng Liu, Krishnendu Chakrabarty
   Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:593-604 [Journal]
   
8. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
   Creating and exploiting flexibility in rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:605-615 [Journal]
   
9. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
   Analysis of power dissipation in embedded systems using real-time operating systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:615-627 [Journal]
   
10. Li Ding 0002, David T. Blaauw, Pinaki Mazumder
    Accurate crosstalk noise modeling for early signal integrity analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:627-634 [Journal]
    
11. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient test access mechanism optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:635-643 [Journal]
    
12. Louis Scheffer
    Some conditions under which hierarchical verification is O(N). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:643-646 [Journal]
    
13. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering for delay minimization under a more general delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:646-651 [Journal]
    
14. Wing Seung Yuen, Evangeline F. Y. Young
    Slicing floorplan with clustering constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:652-658 [Journal]