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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 7

  1. Cesare Alippi
    A probably approximately correct framework to estimate performancedegradation in embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:749-762 [Journal]
  2. Taku Uchino, Jason Cong
    An interconnect energy model considering coupling effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:763-776 [Journal]
  3. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Pattern routing: use and theory for increasing predictability andavoiding coupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:777-790 [Journal]
  4. Elena Gnani, Vincenzo Giudicissi, Radu Vissarion, Claudio Contiero, Massimo Rudan
    Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:791-798 [Journal]
  5. Yu-Shun Guo
    Transient simulation of high-speed interconnects based on thesemidiscretization of Telegrapher's equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:799-809 [Journal]
  6. Priyank Kalla, Maciej J. Ciesielski
    A comprehensive approach to the partial scan problem using implicitstate enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:810-826 [Journal]
  7. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    High-level test compaction techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:827-841 [Journal]
  8. Seongmoon Wang, Sandeep K. Gupta
    DS-LFSR: a BIST TPG for low switching activity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:842-851 [Journal]
  9. Dimitrios Kagaris
    Linear dependencies in extended LFSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:852-859 [Journal]
  10. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
    A new built-in TPG method for circuits with random patternresistant faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:859-866 [Journal]
  11. Congguang Yang, Maciej J. Ciesielski
    BDS: a BDD-based logic optimization system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:866-876 [Journal]
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